Conventional manufacturing process for a Low Temperature Poly Silicon Thin Film Transistor (LTPS TFT in abbreviation) includes subsequently depositing a buffer layer and an amorphous silicon layer on a glass substrate; then performing crystallization treatment on the amorphous silicon layer on the buffer layer to obtain a poly silicon (p-si) layer; subsequently applying a gate insulation layer and a gate metal layer on the poly silicon layer; patterning the gate metal layer to form a gate pattern and implanting ion to the p-si by using the gate pattern as a mask, a desired heavily doped source/drain electrode structure being obtained by controlling the amount of the implanted ion; after that, performing a step of flattening a interlayer insulation layer, a source/drain electrode to obtain the LTPS TFT structure.